1. Field of the Invention
The present invention relates to an integrated circuit for supplying a clock signal and a method for constructing the same, and more specifically to a clock signal supplying integrated circuit, called a "clock tree", internally provided in an LSI having a plurality of power supply voltages, for supplying a clock signal to a circuit for transferring data between memory means driven with different power supply voltages, respectively.
2. Description of Related Art
In an LSI (large-scaled integrated circuit), it is in many cases that a circuit is designed to be constituted of synchronous circuits operating in synchronism with a clock signal. The synchronous circuits have an advantage that a logic can be easily synthesized. On the other hand, if there occurs a phase deviation between clock signals supplied to memory means, respectively, a data transfer cannot be often normally achieved between the memory means.
As a clock signal supplying circuit for making clock signals in phase to each other, a clock signal supplying circuit called a "clock tree" has been known. This clock tree is a clock driver circuit composed of a plurality of buffers connected in the form of a tree, for supplying in-phase clock signals to for example a plurality of memory means, respectively.
Here, assuming that the memory means is constituted of a flipflop, for example, the clock tree is constituted in such a manner that an output of a first stage buffer is connected to an input of each of a plurality of second stage buffers, and an output of each of the second stage buffers is connected to a clock input of each of the same number of flipflops. In the buffers thus connected in the form of the tree, if a clock signal is supplied to an input of the first stage buffer, the clock input of the flipflops connected at a terminating end of the clock tree are supplied with the clock signals in phase to one another.
This clock tree has an advantage that even if the number of flipflops and/or the chip area of the LSI is changed in the course of a designing, it is possible to supply the in-phase clock signals to the flipflops located at the terminating end of the clock tree, by changing a gate length and/or a gate width of transistors included in the buffers, and/or by changing the number of cascaded buffer stages.
However, with an advanced semiconductor manufacturing process, an LSI having a high integration density could has been developed, with the result that the number of transistors internally provided in the LSI is increased, and therefore, the consumed electric power is correspondingly increased. Under this circumstance, there has been adopted an approach of lowering a power supply voltage for some proportion of function blocks internally provided in the LSI, for the purpose of reduce the consumed electric power.
In this case, a plurality of power supply voltages are used in the LSI, and the LSI has been so designed that the circuit location areas are grouped in accordance with the power supply voltages. The clock tree for function blocks driven with a power supply voltage different from that for the other function blocks is prepared independently of the clock tree for the other function blocks, so that the first mentioned function blocks are operated with the different power supply voltage.
In general, a delay time from the moment an input signal of a gate circuit changes to the moment an output signal of the same gate actually changes, varies if the power supply voltage for the same gate is changed. Therefore, in the buffer circuit used in the clock tree, if the power supply voltage changes, the delay time also changes. This situation is illustrated in FIG. 5, which is a timing chart for illustrating the variation of the delay time when the clock tree having two cascaded buffer stages is driven with different power supply voltages.
As shown in the timing chart of FIG. 5, when the same clock signal is supplied to the clock tree driven with a high power supply voltage and to the clock tree driven with a low power supply voltage, the clock signal outputted from the second stage buffer of the clock tree driven with the low power supply voltage is later than the clock signal outputted from the second stage buffer of the clock tree driven with the high power supply voltage, by a time T1. For example, when a circuit shown in FIG. 3 which will be described hereinafter is manufactured in a 0.35 micron process, the time difference T1 between a 3.3V power supply voltage driving and a 2.5V power supply voltage driving becomes 0.6 ns.
In a synchronous circuit for transferring data between a function block driven with a low power supply voltage and the other function block, it is necessary to supply the clock signals having the same frequency and the same phase to not only the flipflops driven with the standard power supply voltage but also the flipflops driven with the low power supply voltage. For this purpose, a delay circuit is used for compensating for the time difference T1, so that the clock signals supplied to all the flipflops are maintained in phase to one another, and therefore, the data can be normally transferred between the function blocks driven with different power supply voltages.
The reason for compensating for the time difference by use of the delay circuit is that: If it is attempted to compensate for the time difference by changing the gate length and/or the gate width of transistors in the buffers of the clock tree, it becomes necessary to change the area of the buffer circuit, with the result that there is possibility that the modified buffer circuits can be no longer located.
Referring to FIG. 3, there is shown a block diagram of one example of the prior art clock signal supplying integrated circuit for supplying in-phase clock signals to function blocks driven with different power supply voltages. The shown prior art example has two kinds of power supplies including a 3.3V power supply and a 2.5V power supply.
In FIG. 3. a clock input terminal 100 is supplied with a clock signal which is either supplied through an external terminal of the LSI or generated in a clock generator internally provided in the LSI. This clock input terminal 100 is connected directly to a clock tree 129, and also, through a delay circuit 127 driven with a 3.3V power supply voltage, to another clock tree 128.
The clock tree 128 is a clock tree for a circuit block driven with the 3.3V power supply voltage, and the clock tree 129 is a clock tree for the circuit block driven with a 2.5V power supply voltage. Flipflop groups 110 to 113, which are circuit blocks driven with the 3.3V power supply voltage, are connected to the clock tree 128, and flipflop groups 123 to 126, which are circuit blocks driven with the 2.5V power supply voltage, are connected to the clock tree 129.
Next, the construction of the clock trees 128 and 129 will be described in detail. The clock tree 128 is composed of 3.3V-operating buffers 101, 102, 103, 104 and 105 (driven with the 3.3V power supply voltage) connected in a tree structure having two cascaded buffer stages. Therefore, the clock tree 128 is constituted of only the circuits operating with the 3.3V power supply voltage. An input of the buffer 101 is connected to an output of the delay circuit 127, and an input of each of the buffers 102 to 105 is connected to an output of the buffer 101. 3.3V-operating flipflops connected to outputs of the 3.3V-operating buffers 102 to 105 are divided into the 3.3V-operating flipflop groups 110 to 113 in such a manner that the same number of flipflops are connected to the output of each buffer.
The 3.3V-operating flipflop group 110 includes 3.3V-operating flipflops 106 to 109, a clock input of each of which is connected to the output of the 3.3V-operating buffer 102. Similarly, a clock input of a plurality of flipflops included in the flipflop groups 111 to 113 are connected to an output of the 3.3V-operating buffers 103 to 105, respectively.
The clock tree 129 is composed of 2.5V-operating buffers 114, 115, 116, 117 and 118 (driven with the 2.5V power supply voltage) connected in a tree structure having two cascaded buffer stages.
Therefore, the clock tree 129 is constituted of only the circuits operating with the 2.5V power supply voltage. An input of the buffer 114 is connected to the clock input terminal 100, and an input of each of the buffers 115 to 118 is connected to an output of the buffer 114. 2.5V-operating flipflops connected to outputs of the 2.5V-operating buffers 115 to 118 are divided into the 2.5V-operating flipflop groups 123 to 126 in such a manner that the same number of flipflops are connected to the output of each buffer.
The 2.5V-operating flipflop group 123 includes 2.5V-operating flipflops 119 to 122, a clock input of each of which is connected to the output of the 2.5V-operating buffer 115. Similarly, a clock input of a plurality of flipflops included in the flipflop groups 124 to 126 are connected to an output of the 2.5V-operating buffers 116 to 118, respectively.
Referring to FIG. 4, there is shown a layout diagram of one example of the layout of the prior art clock signal supplying integrated circuit shown in FIG. 3.
In FIG. 4, in a 3.3V power supply voltage section 301 there are located a ground interconnection 302, a 3.3V power supply voltage interconnection 303, the buffers 101 to 105 of the clock tree 128, the 3.3V-operating flipflops 106 to 109, random circuits 131 and 132 each located between flipflops, and the 3.3V-operating delay circuit 127. On the other hand, in a 2.5V power supply voltage section 325, there are located a ground interconnection 313, a 2.5V power supply voltage interconnection 314, the buffers 114 to 118 of the clock tree 129, the 2.5V-operating flipflops 119 to 122.
In FIG. 4, the 3.3V-operating buffers 101 to 105, the 2.5V-operating buffers 114 to 118, the 3.3V-operating flipflops 106 to 109, the 2.5V-operating flipflops 119 to 122, the 3.3V-operating delay circuit 127 and the random circuits 131 and 132 are layout cells.
Here, the layout cell is a graphical piece indicative of layout information of circuit elements such as a flipflop, a buffer, etc. The layout cell has a ground terminal and a power supply terminal located at opposite ends, respectively. When the layout cell is located, the power supply terminal of the layout cell is connected to the power supply voltage interconnection and the ground terminal of the layout cell is connected to the ground interconnection, by rotating the layout cell by 90 degrees if necessary.
Next, the ground interconnections 302 and 313, the 3.3V power supply voltage interconnection 303 and the 2.5V power supply voltage interconnection 314 will be described in detail.
The ground interconnection 302 are laid out in a periphery of the 3.3V power supply voltage section 301 and to extend in a plurality of horizontal directions, and the 3.3V power supply voltage interconnection 303 are also laid out in a periphery of the 3.3V power supply voltage section 301 and to extend in a plurality of horizontal directions, in such a manner that the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 are paired but separated from each other by a constant spacing.
Similarly, the ground interconnection 313 are laid out in a periphery of the 2.5V power supply voltage section 325 and to extend in a plurality of horizontal directions, and the 2.5V power supply voltage interconnection 314 are also laid out in a periphery of the 2.5V power supply voltage section 325 and to extend in a plurality of horizontal directions, in such a manner that the ground interconnection 313 and the 2.5V power supply voltage interconnection 314 and paired but separated from each other by a constant spacing.
Next, the clock tree and the flipflops in the 3.3V power supply voltage section 301 will be described. Each of the 3.3V-operating flipflops 106 to 109 is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303. Each of the 3.3V-operating buffers 101 to 105 is also located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303. The clock input of each of the 3.3V-operating flipflops 106 to 109 is connected to the output of the 3.3V-operating buffer 102. The input of each of the 3.3V-operating buffers 102 to 105 is connected to the output of the 3.3V-operating buffer 101. Furthermore, although not shown in FIG. 4, the output of the 3.3V-operating buffers 103 to 105 are connected to respective clock inputs of the flipflops in the 3.3V-operating flipflop groups 111 to 113.
Furthermore, the clock tree and the flipflops in the 2.5V power supply voltage section 325 will be described. Each of the 2.5V-operating flipflops 119 to 122 is located between the ground interconnection 313 and the 2.5V power supply voltage interconnection 314. Each of the 2.5V-operating buffers 114 to 118 is also located between the ground interconnection 313 and the 2.5V power supply voltage interconnection 314. The clock input of each of the 2.5V-operating flipflops 119 to 122 is connected to the output of the 2.5V-operating buffer 115. The input of each of the 2.5V-operating buffers 115 to 118 is connected to the output of the 2.5V-operating buffer 114. Furthermore, although not shown in FIG. 4, the output of the 2.5V-operating buffers 116 to 118 are connected to respective clock inputs of the flipflops in the 2.5V-operating flipflop groups 124 to 126.
In addition, a construction between the clock input terminal 100 and the clock trees 128 and 129 will be described in detail. The 3.3V-operating delay circuit 127 is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303. The input of the 3.3V-operating buffer 101 is connected to the output of the delay circuit 127. The clock input terminal 100 is connected to the input of the 2.5V-operating buffer 114 and the input of the 3.3V-operating delay circuit 127.
Furthermore, each of the random circuits 131 and 132 is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303. A data input of the random circuit 132 is connected to a data input terminal 130, and a data output of the random circuit 132 is connected to a data input of the 3.3V-operating flipflop 106. A data output of the 3.3V-operating flipflop 106 is connected to an input of the random circuit 131, which in turn has an output connected to a data input terminal of the 2.5V-operating flipflop 119.
In the circuit shown in FIG. 3, the transfer time of the clock signal from the clock input terminal 100 to the 2.5V-operating flipflop 119 is the total time of an interconnection delay time from the clock input terminal 100 to the input of the 2.5V-operating buffer 114, a gate delay time of the 2.5V-operating buffer 114, an interconnection delay time from the 2.5V-operating buffer 114 to the input of the 2.5V-operating buffer 115, a gate delay time of the 2.5V-operating buffer 115, and an interconnection delay time from the 2.5V-operating buffer 115 to the clock input of the 2.5V-operating flipflops 119 to 122.
Therefore, in order to supply the clock signal, at the same timing, to the clock input of all the flipflops connected to the clock tree 129, it is so constructed that the above mentioned total time assumes the same value at the clock input of the respective flipflops. For this purpose, specifically, the interconnection delay times from the first stage 2.5V-operating buffer 114 to the input of the respective second stage 2.5V-operating buffers 115 to 118 are made equal, the gate delay times of the 2.5V-operating buffers 115 to 118 are also made equal, and further, the interconnection delay times from each of the 2.5V-operating buffers 115 to 118 to the clock input of the respective 2.5V-operating flipflops (119 to 122 and not-shown others) included in the flipflop groups 123 to 126 are made equal.
The gate delay time is determined by the gate length and the gate width of transistors, and the interconnection delay time is determined by the gate length and the gate width of transistors and a wiring capacitance parasitic on the output of the transistor. Therefore, the gate length and the gate width of transistors in the buffers at the same stage level in the cascaded connection structure are made equal, and the wiring capacitance of the interconnections at the same stage level in the cascaded connection structure are made equal. As a result, respective clock signals supplied to the clock input of all the flipflops connected to the clock tree 129, are made to have the same timing, namely, the same phase. This is also true in the clock tree 128.
In the above mentioned manner, the delay times form the input of each of the clock trees 128 and 129 to the clock input of all the flipflops located at the terminating end of the clock tree are made equal to one another, so that the clock signals supplied to the respective flipflops are made in phase to one another.
However, since the clock tree 128 and the clock tree 129 are different from each other in the buffer driving power supply voltage, the clock tree 128 and the clock tree 129 are also different from each other in the gate delay time and in the interconnection delay time. Therefore, the delay time is adjusted by inserting the 3.3V-operating delay circuit 127 between the clock input terminal 100 and the input of the clock tree 128. Thus, the clock signals having the same phase (namely, the same timing) are supplied to the flipflops connected to the clock tree 128 and the flipflops connected to the clock tree 129, respectively.
With the above mentioned arrangement, the data transfer between the blocks driven with different power supply voltages, respectively, exemplified by the data transfer from the 3.3V-operating flipflop 106 through the random circuit 131 to the 2.5V-operating flipflop 119, can be normally realized.
Now, a method for constructing the above mentioned prior art clock signal supplying integrated circuit will be described with reference to FIG. 4.
First, the section 301 for locating 3.3V layout cells therein and the section 325 for locating 2.5V layout cells therein are determined. Then, the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 are laid out in the 3.3V power supply section 301, as shown in FIG. 4, and the ground interconnection 313 and the 2.5V power supply voltage interconnection 314 are laid out in the 2.5V power supply section 325, as shown in FIG. 4. Furthermore, the 3.3V layout cells other than the clock tree are located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 in the 3.3 V power supply section 301, and the 2.5V layout cells other than the clock tree are located between the ground interconnection 313 and the 2.5 V power supply voltage interconnection 314 in the 2.5V power supply section 325.
Thereafter, the clock tree in the 3.3V power supply section 301 is laid out and connected. Here, since the flipflops connected to the 3.3V-operating buffers 101 to 105 have the same construction, the 3.3V-operating buffer 102 will be described as a representative in the following:
First, the 3.3V-operating buffer 102 is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 at a center position among the 3.3V-operating flipflops 106 to 109. Then, the output of the 3.3V-operating buffer 102 is connected to the respective clock inputs of the 3.3V-operating flipflops 106 to 109, by using a detouring wiring if necessary, in such a manner that the wiring capacitances become equal to one another.
Thereafter, the 3.3V-operating buffer 101 is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 at a center position among the 3.3V-operating buffers 102 to 105. Then, the output of the 3.3V-operating buffer 101 is connected to the respective inputs of the 3.3V-operating buffers 102 to 105, by using a detouring wiring if necessary, in such a manner that the wiring capacitances become equal to one another.
The above is a method for laying out and connecting the clock tree in the 3.3V power supply section 301.
Then, the clock tree in the 2.5V power supply section 325 is laid out and connected. Here, since the flipflops connected to the 2.5V-operating buffers 115 to 118 have the same construction, the 2.5V-operating buffer 115 will be described as a representative in the following:
First, the 2.5V-operating buffer 115 is located between the ground interconnection 313 and the 2.5V power supply voltage interconnection 314 at a center position among the 2.5V-operating flipflops 119 to 122. Then, the output of the 2.5V-operating buffer 115 is connected to the respective clock inputs of the 2.5V-operating flipflops 119 to 122, by using a detouring wiring if necessary, in such a manner that the wiring capacitances become equal to one another.
Thereafter, the 2.5V-operating buffer 114 is located between the ground interconnection 313 and the 2.5V power supply voltage interconnection 314 at a center position among the 2.5V-operating buffers 115 to 118. Then, the output of the 2.5V-operating buffer 114 is connected to the respective inputs of the 2.5V-operating buffers 115 to 118, by using a detouring wiring if necessary, in such a manner that the wiring capacitances become equal to one another.
The above is a method for laying out and connecting the clock tree in the 2.5V power supply section 325.
Thereafter, a transfer time in the clock tree laid out and connected in the 3.3V power supply section 301 and a transfer time in the clock tree laid out and connected in the 2.5V power supply section 325 are measured. And, "n" times the gate delay time of the buffer, which can be most approximated to the difference between the two measured transfer times, is found out.
Then, the delay circuit 127 composed of "n" cascaded 3.3V-operating buffers is prepared. The 3.3V-operating delay circuit 127 thus prepared is located between the ground interconnection 302 and the 3.3V power supply voltage interconnection 303 in the 3.3V power supply section 301. The output of the 3.3V-operating delay circuit 127 is connected to the input of the 3.3V-operating buffer 101.
Finally, the clock input terminal 100 is connected to the input of the 2.5V-operating buffer 114 and the input of the 3.3V-operating delay circuit 127. At this time, it is so adjusted, if necessary, by using a detouring wiring, that the transfer time from the clock input terminal 100 to the input of the 3.3V-operating delay circuit 127 becomes equal to the transfer time from the clock input terminal 100 to the input of the input of the 2.5V-operating buffer 114.
Incidentally, for the interconnection, for example, a vertical interconnection is formed of a second level aluminum conductor, and a horizontal interconnection is formed of a first level aluminum conductor. In addition, in order to ensure that the power supply interconnection and the ground interconnection never become short-circuited to each other, the power supply interconnection and the ground interconnection are formed of aluminum conductors of different levels, respectively. Furthermore, the second level aluminum conductor and the first level aluminum conductor are interconnected through through-holes, so that the vertical interconnection is connected to the horizontal interconnection.
However, the following problems have been encountered in the above mentioned prior art clock signal supplying circuit.
As mentioned above, the delay circuit 127 is incorporated for compensating for the difference in the transfer time between the clock tree for the function block driven with the low power supply voltage and the clock tree for the other function block. However, depending upon the diffusion condition of the LSI manufacturing process, and when the operating temperature of the LSI varies, the gate delay time changes, and therefore, the delay time of the delay circuit 127 correspondingly changes, with the result that a phase deviation occurs between the clock signals supplied to the memory means of the function blocks driven with different power supply voltage changes. Because of this, in the synchronous circuit configured to transfer data between the function block driven with the low power supply voltage and the other function block, the normal data transfer becomes impossible if the diffusion condition of the LSI manufacturing process and/or the operating temperature of the LSI vary. In other words, it becomes difficult to design the synchronous circuit.
In the prior art, furthermore, when the layout is modified for changing the function and/or improving the characteristics, the locating positions of the layout cells and their interconnection route change, and further, the locating positions of the clock tree buffers and the memory means and their interconnection route also change correspondingly, with the result that it becomes necessary to measure the transfer time of the clock trees again, and to design the delay circuit anew. In other words, at each time the design is changed and/or the characteristics is improved, the delay circuit must be designed anew, and therefore, the time required for the designing become disadvantageously long.